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Product Identifiers
PublisherSpringer
ISBN-100387718184
ISBN-139780387718187
eBay Product ID (ePID)61062495
Product Key Features
Number of PagesXvi, 300 Pages
Publication NameLow Power Methodology Manual : for System-On-Chip Design
LanguageEnglish
SubjectElectronics / Circuits / Integrated, Electronics / Circuits / General, Electrical, Electronics / General
Publication Year2007
TypeTextbook
AuthorMichael Keating, David Flynn, Rob Aitken, Kaijian Shi, Alan Gibbons
Subject AreaTechnology & Engineering
SeriesIntegrated Circuits and Systems Ser.
FormatHardcover
Dimensions
Item Height0.4 in
Item Weight48.7 Oz
Item Length9.3 in
Item Width6.1 in
Additional Product Features
Intended AudienceScholarly & Professional
LCCN2007-928355
Dewey Edition22
Number of Volumes1 vol.
IllustratedYes
Dewey Decimal621.381
Table Of ContentStandard Low Power Methods.- Multi-Voltage Design.- Power Gating Overview.- Designing Power Gating.- Architectural Issues for Power Gating.- A Power Gating Example.- IP Design for Low Power.- Frequency and Voltage Scaling Design.- Examples of Voltage and Frequency Scaling Design.- Implementing Multi-Voltage, Power Gated Designs.- Physical Libraries.- Retention Register Design.- Design of the Power Switching Network.
Synopsis"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe such] a] low-power methodology with a practical, step-by-step approach." Richard Goering, Software Editor, EE Times "Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion." Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies "The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs." Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc. "Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management." Nick Salter, Head of Chip Integration, CSR plc., This book provides a practical guide for engineers doing low power System-on-Chip (SoC) designs. It covers various aspects of low power design from architectural issues and design techniques to circuit design of power gating switches. It also describes some well established techniques and then details the latest approaches to low power design. These leading edge techniques include power gating and adaptive voltage scaling. In addition to providing a theoretical basis for these techniques, the book addresses the practical issues of implementing them in today's designs with today's tools. All of the methods used have been proven in test chips jointly developed by Synopsys and ARM., "Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach." Richard Goering, Software Editor, EE Times "Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion." Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies "The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs." Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc. "Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management." Nick Salter, Head of Chip Integration, CSR plc.
LC Classification NumberTK7867-7867.5
