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- KurzbeschreibungGallium nitride (GaN)-based High Electron Mobility Transistors (HEMTs) for high voltage, high power switching and regulating for space applications are studied in this work. Efficient power switching is associated with operation in high OFF-state blocking voltage while keeping the ON-state resistance, the dynamic dispersion and leakage currents as low as possible. The potential of such devices to operate at high voltages is limited by a chain of factors such as subthreshold leakages and the device geometry. Blocking voltage enhancement is a complicated problem that requires parallel methods for solution; epitaxial layers design, device structural and geometry design, and suitable semiconductor manufacturing technique. In this work physical-based device simulation as an engineering tool was developed. An overview on GaN-based HEMTs physical based device simulation using Silvaco-ôATLASö is given. The simulation is utilized to analyze, give insight to the modes of operation of the device and for design and evaluation of innovative concepts. Physical-based models that describe the properties of the semiconductor material are introduced. A detailed description of the specific AlGaN/GaN HEMT structure definition and geometries are given along with the complex fine meshing requirements. Nitride-semiconductor specific material properties and their physical models are reviewed focusing on the energetic band structure, epitaxial strain tensor calculation in wurtzite materials and build-in polarization models. Special attention for thermal conductivity, carriersÆ mobility and Schottky-gate-reverse-bias-tunneling is paid. Empirical parameters matching and adjustment of models parameters to match the experimental device measured results are discussed. An enhancement of breakdown voltage in AlxGa1-xN/GaN HEMT devices by increasing the electron confinement in the transistor channel using a low Al content AlyGa1-yN back-barrier layer structure is systematically studied. It is shown that the reduced sub-threshold drain-leakage current through the buffer layer postpones the punch-through and therefore shifts the breakdown of the device to higher voltages. It is also shown that the punch-through voltage (VPT) scales up with the device dimensions (gate to drain separation). An optimized electron confinement results both, in a scaling of breakdown voltage with device geometry and a significantly reduced sub-threshold drain and gate leakage currents. These beneficial properties are pronounced even further if gate recess technology is applied for device fabrication. For the systematic study a large variations of back-barrier epitaxial structures were grown on sapphire, n-type 4H-SiC and semi-insulating 4H-SiC substrates. The devices with 5 ?m gate-drain separation grown on n-SiC owning Al0.05Ga0.95N and Al0.10Ga0.90N back-barrier exhibit 304 V and 0.43 mW Î cm2 and 342 V and 0.41 mW Î cm2 respectively. To investigate the impact of AlyGa1-yN back-barrier on the device properties the devices were characterized in DC along with microwave mode and robustness DC-step-stress test. Physical-based device simulations give insight in the respective electronic mechan
- AutorEldad Bahat-Treidel
- AusgabeReihenbandnummer 22.
- VerlagCuvillier Verlag
- Seiten220 Seiten
- Gewicht296 g
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